Silicon Thinking | IoT-Ready SOC

Dassault Systèmes’ Silicon Thinking solution experience covers the end-to-end semiconductor product development.


It provides a semiconductor template with

  • optimum resources allocation and monitoring
  • collaborative management of Semi IP
  • modular (Rules-Driven) Hardware & Software
  • hierarchical and dynamic BOM (BOI)
  • integrated simulation life-cycle management for device validation & verification
  • continuous integration of backend data with integrated analytics (Pinpoint)
  • enables researchers to model and optimize a range of materials for semiconductors.


  • Achieve higher efficiency and zero re-spins in developing IOT-ready Systems-On-Chip
  • True Enterprise Requirements Driven Semiconductor PLM system
  • Semiconductor Template Driven Workspace, Project, Dashboard for Optimum Resources Allocation Execution Monitoring.
  • Modular (Rules-Driven) Hardware & Software, Hierarchical and Dynamic BOM (BOM).
  • Integrated Simulation Life-Cycle Management for SOC Validation & Verification.
  • 3rd Generation of Collaborative Management of Semi IP
  • RTL / Modules / Frond-end / Back-end / IP Security & Protection
  • Semiconductor-enforced Rules at DDM / WIP Level : SITAR as Industry Proven methodology
  • Continuous integration of backend data with integrated analytics (Pinpoint)
  • Provides real time traceability to project goals unlike static based document driven systems
  • Speeds up deployment by providing templates designed and proven by semiconductor companies
  • Reduces errors throughout the SoC development cycles by quantifying rules for hand off and qualifying criteria for successful completion of workflow tasks
  • Prevents costly respins or time consuming late stage changes by providing instant notification to changes in requirements, design files, simulation test benches or IP and PDK’s.
  • Streamlines SoC design productivity by providing analytics, searching, reporting, and integrated issue and defect
  • Industry production proven DDM technology
  • Streamlines WIP workflow by providing “Invisible governance” of the project.
  • Reduces SoC Design closure by providing a true collaborative environment for logic and physical designers to work together to achieve design closure with “Instant access” to real time semiconductor design data.