ASIC/SOC Design Teams


Pinpoint helps reduce risk and lower overall project costs by providing ASIC, SOC and FPGA design teams with real time progress and status information about each phase of the design cycle. Pinpoint assimilates data from multiple sources – synthesis, STA, power, layout, physical verification, etc. – and intelligently displays this data in customizable dashboards that provide a holistic view of the progress of each phase of the design and maturity of the overall design.


  • No more struggling with designs being 95% complete for 30% of design cycle time - comprehensive trend analysis and collated reporting in one dashboard displays real progress to design closure
  • Out-of-the-box timing reports provide detailed and filterable lists of timing paths to facilitate a structured approach to STA diagnostics
  • Reporting format enables designers to run design experimentations by uniquifying each run so you can identify an optimal set of constraints as a starting point
  • View layout, DRC, PV reporting and metrics in Pinpoint, instead of ‘checking out’ expensive APR tools

Key Features

Web Based Analysis for Collaborative Design

  • Pinpoint extracts design information from tool reports, log files and LEF/DEF so it’s non-disruptive to your design flow
  • Reports and metrics are displayed as web based, real time updates, so designers can spend more time debugging instead of preparing for design reviews
  • Share links to dynamic reports or layout views across geographically dispersed design centers and collaborate in real time on web meetings to resolve design issues quickly

Powerful Integrated Analytics Capability

  • Designers can view full chip and block level metrics, for individual functions, i.e. STA, or view metrics from multiple sources in one report - e.g. view inter-or intra-block timing paths with hierarchy over a layout view

‘Out of the Box’ Ease of Use

  • Pinpoint is tool agnostic; it imports data from any EDA vendor tool flow or point tool
  • Out of the box support for common EDA tools with many pre-configured reports enables immediate reporting on design flow progress

Connectivity Aware Layout for Detailed Reporting

  • Connectivity aware processing engine understands every instance in your design, including hierarchy, so it can provide interactive metrics about your design – including DRC violations, location of timing path violations, etc.

API for Integrating Custom Reporting

  • Flexible API enables rapid integration of existing in-house developed metrics or 3rd party produced metrics with Pinpoint
  • New custom reports can easily be created from existing data, or as new tools are added to your design flow